Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell (e.g., floating gate memory cell) that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage node, such as a floating gate or charge trap, or other physical phenomena, determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a NAND type flash memory array architecture 100 wherein the floating gate memory cells 102 of the memory array are logically arranged in a matrix of rows and columns. The memory cells 102 of the array are also arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each, where the memory cells in a string are connected together in series, source to drain, between a common source line 114 and a data line 116, often referred to as a bit line. The array is then accessed by a row decoder activating a row of floating gate memory cells (e.g., 120) by selecting a particular access line (e.g., 1184), often referred to as a word line, connected to their gates. In addition, bit lines BL1-BL4 116 can also be driven high or low depending on the current operation being performed. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
Bit lines BL1-BL4 116 are coupled to sensing devices (e.g., sense amplifiers) 130 that detect the state of each cell by sensing voltage or current on a particular bit line 116. The word lines WL7-WL0 118 select the individual memory cells 102 in the series strings to be written to or read from and operate the remaining memory cells in each series string in a pass through mode. Each series string of memory cells is coupled to a source line 114 by a source select gate 110 and to an individual bit line BL1 1161 by a drain select gate 1041, for example. The source select gates 110 are controlled by a source select gate control line SG(S) 112 coupled to the source select gate control gates. The drain select gates, such as 104, are controlled by a drain select gate control line SG(D) 106.
During a typical programming operation performed on a memory array as illustrated in FIG. 1, a particular word line is selected for programming, such as WL4 1184, for example. During a programming operation alternate bit lines are enabled and inhibited from programming. For example, even numbered bit lines might be enabled for programming memory cells coupled to even numbered bit lines while the odd numbered bit lines are inhibited from programming memory cells coupled to the odd numbered bit lines. A subsequent programming operation then inhibits the even numbered bit lines and enables the odd numbered bit lines. Bit lines are typically enabled for programming of their associated memory cells by applying 0V to those bit lines. Bit lines are typically inhibited from programming their associated memory cells by applying a supply voltage, Vcc (e.g., 2.3V), to those bit lines, for example. Another programming method employs biasing one or more of the bit lines during a programming operation to a level that does not inhibit programming but effectively reduces the rate of programming. For example, a bit line might be biased to a voltage of 0.5V to slow programming of a memory cell coupled to the bit line during a programming operation.
FIG. 1 further illustrates an example of bias potentials that might be applied during a programming operation performed on a selected row (e.g., WL4 1184) of memory cells. During the example programming operation, the channel region 1221,3 is biased to 0V as a result of the 2.5V present on the SG(D) line 106 which enables select gates 1041,3. The channel region 1222,4 is not biased to the potential on BL2, BL4 1162,4 due to the Vcc potential present on those bit lines which places the select gates 1042,4 in an off condition. The source select gates 110 of each string are biased by the SG(S) voltage (e.g., 0.5V) in a manner as to render them in an off condition. In the example of FIG. 1, a VPASS voltage is applied to each unselected word line 1187-1185,1183-1180. VPASS might be 10V, for example. The VPASS voltage is sufficient to turn the unselected memory cells on but is not high enough to cause programming of those memory cells. A programming potential VPGM is applied to the word line selected for programming, such as WL4 1184, for example. VPGM typically comprises a series of increasing voltage pulses throughout the programming operation. VPGM programming pulses might range from 12V to 25V, for example. As a result of the VPASS voltage placed on each unselected word line and the VPGM voltage placed on the selected word line, the channel region 1222, indicated by dashed lines, of the BL2 1162 string is boosted up. For example, the channel region 1222 might be boosted up to a potential of 8V as a result of the drain select gate 1042 being in an off state. The channel region 1221 is held at the 0V potential of BL1 1161 because drain select gate 1041 is in an on state. However, the drain select gates 1042,4 might still leak charge from channel regions 1222,4 (boosted to 8V) to BL2, BL4 1162,4 which are biased at Vcc (e.g., 2.3V). This leakage of charge through drain select gates 1042,4 can cause undesirable effects on memory cells that are not selected for programming. These undesirable effects are referred to as program disturb effects which can alter the programmed state of memory cells to an unintended state.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art, for example, for alternate biasing schemes that serve to mitigate the effects of program disturb.